Integrated circuit and method for making the same

ABSTRACT

An integrated circuit has at least one semiconductor device for storing charge that includes at least one elementary active component and at least one elementary storage capacitor. The device includes a substrate having a lower region containing at least one buried capacitive elementary trench forming the elementary storage capacitor, and an elementary well located above the lower region of the substrate and isolated laterally by a lateral electrical isolation region. The elementary active component is located in the elementary well or in and on the elementary well. The capacitive elementary trench is located under the elementary active component and is in electrical contact with the elementary well. In one preferred embodiment, the lateral electrical isolation region is formed by a trench filled with a dielectric material and has a greater depth than that of the elementary well. Also provided is a method for fabricating an integrated circuit that includes a semiconductor device for storing charge.

[0001] The invention relates to integrated circuits and moreparticularly to analog devices for storing charge, in particular analogmemory cells or light sensors.

[0002] Electronic memories usually operate with two logic levels 1 and0. For dynamic random access memory (DRAM memory), these levelscorrespond to the charged or uncharged state of a capacitor. Reading thememory cell destroys the state of this memory cell since the chargesstored in the capacitor are used as a read signal. In addition, for thesake of the memory cell density, the capacitance of the capacitor islow, and it is then impossible to differentiate several charge levels ofthe capacitor. Moreover, because of the various leakage currentsassociated with the control devices, the charge on the capacitordecreases and is not stable with time.

[0003] A memory cell of the DRAM type must be as small as possible forthe sake of density. It consists of an access transistor controlling thecharging or the discharging of a capacitor. This capacitor must, on theone hand, have a maximum capacitance and, on the other hand, occupy aminimum surface. Currently, the capacitor is made either in the siliconsubstrate or in the upper interconnect layers of the integrated circuit.

[0004] In the first case, the capacitor is located at the side of theaccess transistor. In the second case, the capacitor occupies a largevolume above the transistor, a volume which cannot be used to makeinterconnections in the integrated circuit.

[0005] In both cases, the density of the memory cell, that is to say itsoverall size, is affected thereby.

[0006] The aim of the invention is to provide a solution to thisproblem.

[0007] One aim of the invention is to propose a device having a minimumsurface and capable of storing charge, to provide a very long retentiontime for the stored charge, to allow the stored charge to be readwithout loss of information and to evaluate the amount of stored chargein an analog manner.

[0008] One of the aims of the invention is thus to propose the use ofsuch a device as an analog memory cell providing non-destructive readingof the stored information.

[0009] Another aim of the invention is to propose the use of such adevice, once matrix-configured, as an image sensor allowing a lightimage to be transformed into analog electrical information. Moreprecisely, the image is transferred into a matrix, of which each elementrepresents, in the form of analog electrical information, one element(pixel) of the original image. The writing operations of this matrix donot destroy the imprint of the previously written image, which allowselementary operations such as the superposition of two images to becarried out at the sensor.

[0010] The invention therefore proposes an integrated circuit,comprising a semiconductor device for storing charge having at least oneelementary storage capacitor and one elementary active componentenabling the stored charge to be measured. According to a generalcharacteristic of the invention, the device comprises a substrate havinga lower region containing at least one buried capacitive elementarytrench forming said elementary storage capacitor and an elementary welllocated above said lower region of the substrate and isolated laterallyby a lateral electric isolation region. The elementary active componentis made in the elementary well or in and on the elementary well and saidcapacitive elementary trench is located under the elementary activecomponent and is in electrical contact with the elementary well.

[0011] In other words, the device according to the invention comprisesan elementary active component with a capacitor of the buried trenchtype located not at the side of the elementary component but under theelementary component. The overall size is therefore reduced. The firstelectrode of the capacitor is the substrate and the second electrode isa conductor filling the trench. This capacitor is located below theelementary well of the elementary active component, and is connected tothis elementary well by direct contact between the internal electrode ofthe capacitor and the elementary well. The surface area of theelementary well-substrate junction is reduced by the presence of theburied capacitor.

[0012] This elementary active component may in particular be a MOSFETtransistor, a JFET transistor, or else a resistor.

[0013] The lateral isolation zone is advantageously formed by a trenchfilled with a dielectric and has a greater depth than that of theelementary well.

[0014] The region extending between the elementary capacitive trench andthe lateral isolation zone forms an elementary PN junction between theelementary well and said lower substrate region. And the area of saidelementary junction is advantageously lower than the contact surface ofsaid elementary capacitive trench with the elementary well.

[0015] According to one embodiment, the elementary trench comprises anupper region in contact with the elementary well and having the sametype of conductivity as that of the elementary well.

[0016] According to one embodiment, the substrate is made of silicon,and the capacitive trench comprises an inner region of doped silicon,partially enveloped by an isolating wall laterally separating said innerregion of the substrate, and surmounted by the upper region made ofdoped silicon.

[0017] The device can be used as an analog memory cell.

[0018] In this case, according to one embodiment, the storage devicecomprises several adjacent elementary active components associated withseveral buried capacitive elementary trenches, respectively, inrespective electrical contact with several elementary wells, said lowerregion of the substrate forming an isolating well with respect to therest of the substrate, so as to form an analog memory plane which can beerased by applying a chosen voltage to the isolating well.

[0019] The device can also be used as a light sensor.

[0020] In the latter case, according to one embodiment, the storagedevice comprises several adjacent elementary active componentsassociated with several buried capacitive elementary trenches,respectively, in respective electrical contact with several elementarywells, so as to form a light sensor, each pixel of which is formed by anelementary active component and by the associated elementary trench.

[0021] The processes for fabricating semiconductor components maydestroy the crystal continuity of the surface of a portion of theinitial single-crystal semiconductor substrate. This is particularly thecase when making a trench. At the location of the trench, thesemiconductor substrate has a different material without a crystalstructure. Consequently, the surface of that portion of the substrateoccupied by the trench cannot be used to produce semiconductor devices.

[0022] The invention also makes it possible to provide a solution tothis problem.

[0023] One aim of the invention is to allow the production of asingle-crystal substrate enabling the subsequent formation of anepitaxial layer of silicon free of crystal defects and in which thecontrol transistor or transistors of the device will be made.

[0024] The invention therefore also proposes a process for fabricatingan integrated circuit comprising a semiconductor device for storingcharge having an elementary active component, for example a controltransistor, and an elementary storage capacitor. According to a generalcharacteristic of the invention,

[0025] a) an initial single-crystal substrate locally having acapacitive elementary trench emerging at the surface of the initialsubstrate and forming a discontinuity in the crystal lattice isprepared,

[0026] b) the initial substrate is recessed at the elementary trench,

[0027] c) the crystal lattice is amorphized around the periphery of therecess,

[0028] d) a layer of amorphous material having the same chemicalcomposition as that of the initial substrate is deposited on thestructure obtained in the previous step,

[0029] e) the structure obtained in the previous step is thermallyannealed in order to recrystallize the amorphous material so as to becontinuous with the single-crystal lattice of the initial substrate,

[0030] f) an upper substrate layer is grown by epitaxy,

[0031] g) an elementary well located above and in contact with thecapacitive elementary trench is defined in said upper substrate layerand the elementary active component is made in and on said elementarywell.

[0032] According to one implementation mode, the process comprises,prior or subsequent to step e), a surface planarization step, forexample a chemical-mechanical polishing operation.

[0033] The definition of the elementary well comprises, for example, theproduction of isolation regions, implantation and annealing.

[0034] According to one implementation mode, the amorphization stepcomprises localized ion implantation around the recess by means of amasking operation.

[0035] According to one implementation mode, in step a), a first layerof a first material and a second layer of a second material aredeposited in succession on the initial substrate, then an elementarytrench is etched, which is filled with a fill material,

[0036] and, in step b), the first layer and an upper portion of theelementary trench fill material are selectively etched with respect tosaid second layer so as to form lateral cavities and said recess at thecrystal discontinuity, and said second layer is removed.

[0037] In step a), the filling of the elementary trench advantageouslycomprises the following steps:

[0038] the walls of the elementary trench are lined with oxide bythermal oxidation;

[0039] highly doped polycrystalline silicon is deposited in theelementary trench so as to fill it;

[0040] the polycrystalline silicon deposited previously is etched sothat the fill level of the elementary trench is below the surface of theinitial substrate.

[0041] Other advantages and characteristics of the invention will appearon examining the detailed description of embodiments and ofimplementation modes, which are in no way limiting, and the appendeddrawings in which

[0042]FIGS. 1a to 1 i illustrate schematically the main steps of aprocess according to the invention together with embodiments of astorage device according to the invention, and

[0043]FIGS. 2 and 3 illustrate schematically two other embodiments of astorage device according to the invention.

[0044] The starting substrate of the process of the invention, or theinitial substrate, is illustrated in FIG. 1a and in this case comprisesan elementary trench. In this case, the initial substrate 1 is n-doped.The elementary trench may be made, according to one implementation ofthe process of the invention, by firstly depositing a layer of siliconoxide 2 on the initial single-crystal silicon substrate 1. The thicknessof this layer 2 may vary between 0.01 micron and 1 micron, and ispreferably about 2000 Å.

[0045] Next, a layer of silicon nitride 3 is deposited on the oxide 2.The thickness of this layer 3 may also vary between 0.01 micron and 1micron, and is also preferably about 2000 Å.

[0046] Next, first of all the nitride 3 and the oxide 2, then finallythe single-crystal silicon of the substrate 1 are etched in aconventional manner using a photolithography operation, in order to formthe elementary trench 4.

[0047] The elementary trench 4 has a depth of about 6 μm and a width,preferably less than 1 μm, for example equal to 0.3 μm.

[0048] Next, a controlled thermal oxidation is carried out so as todeposit a layer of silicon oxide 8 of a thickness between 40 and 1000 Å,preferably between 50 and 300 Å, on the walls of the elementary trench4. The device illustrated in FIG. 1a is obtained.

[0049] Next, heavily p⁺-doped polycrystalline silicon 9 is deposited onthe wafer so as to fill the elementary trench 4. The doping of thesilicon is carried out in situ.

[0050] A device as illustrated in FIG. 1b is obtained.

[0051] Next, the polycrystalline silicon 9 deposited beforehand isetched, at least so as to remove it from the surface of the wafer.Moreover, this etching is carried out until the level of thepolycrystalline silicon in the elementary trench 4 is below the surfaceof the initial substrate 1.

[0052] The next step consists of a controlled deoxidation, essentiallyso as to form, under the silicon nitride layer 3, two lateral cavitiesof given width in the oxide layer 2, as illustrated in FIG. 1c. Some ofthe silicon oxide 8 in the trench 4 is also removed.

[0053] This deoxidation is carried out by isotropic etching usinghydrofluoric acid or else by isotropic plasma etching using fluorine.The device illustrated in FIG. 1c, in which the trench is lined with asilicon oxide layer 8 whose height is less than the height of the dopedpolycrystalline silicon layer 9 in the elementary trench 4, is thenobtained. Two lateral cavities of given width appear below the siliconnitride layer 3 and in the silicon oxide layer 2.

[0054] Next, the silicon nitride mask 3 is conventionally removed.

[0055] The exposed silicon is then amorphized.

[0056] The silicon exposed at this stage of the process is thesingle-crystal silicon of the substrate 1 together with the emergentportion of doped polycrystalline silicon 9 in the elementary trench 4.Thus, amorphous silicon regions labeled 6 and 6 a are created (FIG. 1d).

[0057] The localized simultaneous amorphization of the regions 6 and 6 ais self-aligned on the elementary trench. The amorphization is carriedout conventionally by destroying the crystal lattice of the silicon andof the polycrystalline silicon 6 a, for example by the implantation ofheavy particles such as ions. Within the context of the invention, itwill be especially preferred to implant fluoride ions.

[0058] Next, an amorphous silicon layer 7 is deposited over the entiresurface of the wafer so as at least to fill the lateral cavities and therecess above the elementary trench 4. The amorphous layer 7 depositedtherefore has, in this case, a role of connecting the regions 6 and 6 aand resealing the surface. The amorphous silicon is depositedconventionally at low temperature. For example, it is possible to use anLPCVD (low-pressure chemical vapor deposition) furnace, injecting silaneat a sufficiently low temperature, for example less than 600° C.,typically less than 400° C. The device illustrated in FIG. 1d is thusobtained, in which, in an elementary trench 4 etched in a substrate 1, apolycrystalline silicon block 9 is partially enveloped in a siliconoxide layer 8. The height of this block, less than that of theelementary trench 4, is also less than the height of the silicon oxideenvelope 8. This element is surmounted by an amorphous silicon regioncomprising the amorphized silicon regions 6 and 6 a and the amorphoussilicon 7 deposited.

[0059] A thermal annealing operation is carried out so as to restore thecrystal structure of the amorphous silicon. The thermal annealing allowsthe amorphous silicon to recrystallize, by the epitaxial regrowth of theamorphous silicon 6, 7 starting from the single-crystal silicon of theinitial substrate 1. The restructuring of the single-crystal siliconlattice results in FIG. 1e in which the previous amorphous silicon layernow merges with the single-crystal silicon of the substrate 1.

[0060] It should be noted here that, according to the invention, thezone 6 is spatially limited, and the boundary between this zone 6 andthe substrate 1 is easily localized by ion implantation. Moreover, thisboundary is a “soft” boundary, that is to say that the change of thesingle crystal Si state to the amorphous Si state is very gradual. Thesecharacteristics lead to a good recrystallization yield of the zone 6,and to recrystallization without defects, that can be difficult toobtain with a large surface to be recrystallized.

[0061] Furthermore, the amorphization of the zone 6 b is makes itpossible to prevent a “backtrack” of crystalline defects in the singlecrystal layer from the polycrystalline silicon.

[0062] Next, a chemical-mechanical polishing operation is carried out,stopping on the silicon oxide layer 2 in order to remove therecrystallized silicon layer on the surface of the wafer. The siliconoxide layer 2 is then conventionally removed. Next, in order toplanarize the surface, the wafer is subjected to a finalchemical-mechanical polishing operation.

[0063] After the steps of making the surface of the substrate uniform, afinal single-crystal silicon substrate 10 is obtained, illustrated inFIG. 1f, the perfectly planar and uniform single-crystal surface ofwhich allows the defect-free epitaxial growth of single-crystal silicon.The thickness of the substrate 10 above the elementary trench is about0.2 microns. Moreover, the substrate comprises a buried capacitiveelementary trench TRC consisting of highly doped polycrystalline silicon90 partially enveloped by a silicon oxide wall 8 separating it laterallyfrom the substrate 1. Above this buried capacitive elementary trench andin the substrate 1, there is a doped region 1 a, of the sameconductivity as the polycrystalline silicon 90. This region correspondsto the amorphized polycrystalline silicon region 6 a and to the portionof silicon 7 doped by diffusion of dopants during annealing.

[0064] The localized destruction, according to the invention, of thecrystal lattice before its restoration is particularly advantageous forcapacitive trenches since it allows the polycrystalline silicon 90 (theentire capacitor) to be buried by controlled etching of the sidewalloxide 8, without the need for providing an additional oxide.

[0065] The process continues with the epitaxial growth on the surface ofthe substrate 10, of an upper substrate layer 12, made of p-dopedsilicon (FIG. 1g), and having a thickness of about 1 μm. It is in thislayer 12 that the control transistor T of the device DIS will be made.The substrate SB, made from the substrate 10 and from the layer 12,incorporates the capacitive elementary trench TRC.

[0066] More specifically, as illustrated in FIG. 1h, shallow isolatingside regions STI having a depth of about 1.5 μm are made around theburied elementary trench TRC. In the volume of silicon delimited bythese regions STI, a p-doped elementary well CS is made by ionimplantation followed by diffusion and annealing. The implantation is,for example, an implantation of boron at 10¹³ at/cm² at an energy of 80keV. The annealing is carried out, for example, at 950° C. for 20minutes. The depth of this elementary well CS is such that electricalcontinuity is provided between the elementary well and the upper region1 a of the p-doped elementary trench. The depth of the regions STI issufficient to isolate two adjacent elementary wells.

[0067] Inside the volume delimited by the regions STI, the controltransistor T, in this case of the NMOS type, is formed in a quiteconventional manner. More specifically, after having made the sideisolation regions STI, the gate oxide, then the gate polysilicon whichis etched to form the isolated gate G of the transistor, are formed.

[0068] The drain and source regions are made conventionally by doubleimplantation before and after forming isolating spaces ES flanking thegate. A conventional siliciding step makes it possible to metallize thedrain, source and gate regions so as to provide electrical contacts.

[0069] Finally, an NMOS transistor, whose elementary well CS is isolatedfrom the substrate by a p-n elementary junction and by the dielectriclayer 8 of the elementary trench TRC is therefore obtained.

[0070] The capacitive elementary trench under the well makes it possibleto

[0071] produce an MOS transistor close to the minimum dimensions, thewell CS of this transistor being directly connected to an electrode ofthe capacitive elementary trench without using the metal interconnect,

[0072] increase the capacitance between the elementary well and thesubstrate,

[0073] decrease the surface area of the “p well/n substrate” elementaryjunction, therefore to decrease the currents in this elementary junctionand in particular the leakage currents.

[0074] The device may thus be advantageously used as an analog memorycell or even as an elementary light sensor.

[0075] When the device DIS is used as an analog memory cell, it operateswith three cycles, that is a write cycle, a cycle for retaining thestored information and a read cycle.

[0076] During writing, the elementary well CS is biased at a givennegative voltage. More specifically, the substrate is biased, forexample, at 0 V, the drain −1 V, and the source and the gate are leftfloating. Electrons are then injected into the floating well CS and theybias it to said negative voltage, for example −1 V.

[0077] During the retention, the charge thus stored is considerablesince the capacitance of the well with respect to the substrate is high.This charge only disappears very slowly since the leakage currents, inparticular those with respect to the substrate, are low.

[0078] The characteristics of the control transistor depend directly onthe potential of the well. In particular, for an n-type MOS transistor,the threshold voltage of the transistor increases when the potential ofthe well decreases. Thus, for a gate bias greater than the thresholdvoltage corresponding to a zero well potential, the drain current is afunction of the well voltage for a given drain voltage.

[0079] Knowledge of this drain current makes it possible to measure thewell voltage, and consequently to measure the amount of charge stored.This measurement is an analog measurement and does not destroy thecharge stored in the floating well.

[0080] In FIG. 1i, several (for example three) adjacent pairs oftransistors T1-T3 and of associated buried capacitive trenchesTRC1-TRC3, are shown schematically. Each pair forms a pixel of a lightsensor.

[0081] With respect to the implementation mode detailed above, theinitial substrate is p-doped. Consequently, a double-well structurecomprising an n-doped diffused isolation well CD is provided. Theelementary wells CS1-CS3 of the transistors are then formed as indicatedabove and are mutually separated by isolation regions STI. An additionaln-type well CSN is also made by implantation making it possible to biasthe diffused well CD.

[0082] The matrix-configured sensor with several pixels (in practiceseveral million pixels) operates with three cycles, that is a prechargecycle, a cycle for acquiring the light information, and a read cycle.

[0083] During precharging, the potential of the well of each pixel canbe set, as explained above, by the bias of the drain (for example −1 V).Another advantageous possibility for this type of sensor consists inbiasing the source, the gate and the drain of the transistor to 0 V, andin biasing the well CSN (therefore the wells CS1-CS3) successively at −1V then at 0 V.

[0084] With this solution, all the elementary wells CSi are found tohave a potential close to −1 V when the voltage of the well CSN (or CD)goes to 0 V. The potentials of the wells do not vary with time for thesame reasons as those explained above.

[0085] When acquiring the light information, the source, gate and drainof each transistor are left floating and the well CSN is biased at 0 V.When a light image is formed on the surface of the sensor, each pixel isilluminated differently. In particular, the light flux increases theleakage current of each well CSi/well CD junction. As a result, there isan increase in the potential of each elementary well CSi which dependson the illumination.

[0086] The previously formed image is read by measuring the voltage ofthe elementary wells CSi through the current of each control transistor.This measurement is an analog measurement and is not destructive. Themeasurement of the light intensity is consequently an analogmeasurement.

[0087] It is also possible, if the precharge cycle is not carried out,to compare two successive images in order to measure, for example, theirdifferences. The methods of compressing a digitized image are thusfacilitated.

[0088] The structure illustrated in FIG. 1i may also be used as ananalog memory plane that can be erased by applying a chosen voltage tothe isolation well CD.

[0089] Although the embodiments and implementational modes which havejust been described use an MOS transistor as elementary activecomponent, it would be possible to provide any active component allowingmeasurement of the stored charge, especially a resistor or a junctionfield effect transistor (JFET).

[0090] In this regard, FIG. 2 illustrates schematically a charge storagedevice whose elementary active component is a resistor.

[0091] This resistor R is, for example, a layer of n-doped silicon,whose value of resistance depends on the number of (electron) carriersin this resistor. Thus, by way of indication, if the dopantconcentration is less than 5×10¹⁸ at/cm³, the potential differencebetween the resistor and the elementary well CS will create a depletionin the resistance due to carriers. The value of this resistance isconsequently correlated with that of the potential of the elementarywell.

[0092] In this variant, the value of the resistance that can be easilymeasured conventionally is generally an image of the potential of theelementary well and therefore of the amount of charge stored.

[0093] This device is consequently very simple to produce andeconomical.

[0094]FIG. 3 illustrates schematically a charge storage device whoseelementary active component is a JFET transistor. In this case, then-doped resistive layer under the gate of the transistor is clamped bythe potential of the gate and by the potential of the elementary wellCS.

[0095] The measurement of the current flowing in the JFET transistorprovides an image of the amount of charge stored.

[0096] This device offers the advantage of being higher performing, inparticular in terms of sensitivity, than the one illustrated in FIG. 2.

1. An integrated circuit, comprising a semiconductor device for storingcharge having at least one elementary storage capacitor and oneelementary active component enabling the stored charge to be measured,characterized in that the device comprises a substrate having a lowerregion containing at least one buried capacitive elementary trenchforming said elementary storage capacitor, and an elementary welllocated above said lower substrate region and isolated laterally by alateral electric isolation region, in that the elementary activecomponent is made in the elementary well or in and on the elementarywell and in that said capacitive elementary trench is located under theelementary active component and is in electrical contact with theelementary well.
 2. The circuit according to claim 1, characterized inthat the lateral isolation region is formed by a trench filled with adielectric and has a greater depth than that of the elementary well. 3.The circuit according to claim 1 or 2, characterized in that the regionextending between the elementary capacitive trench and the lateralisolation zone forms an elementary pn junction between the elementarywell and said lower substrate region, the area of said elementaryjunction being lower than the contact surface of said elementarycapacitive trench with the elementary well.
 4. The circuit according toone of the preceding claims, characterized in that the elementary trenchcomprises an upper region in contact with the elementary well and havingthe same type of conductivity as that of the elementary well.
 5. Thecircuit according to claim 4, characterized in that the substrate ismade of silicon, in that the capacitive elementary trench comprises aninner region of doped silicon, partially enveloped by an isolating walllaterally separating said inner region of the substrate, and surmountedby said upper region made of doped silicon.
 6. The circuit according toclaim 5, characterized in that the substrate has n-type conductivity, inthat the inner region and the upper region of the capacitive elementarytrench as well as the elementary well have p-type conductivity.
 7. Thecircuit according to one of the preceding claims, characterized in thatthe elementary active component is a resistor.
 8. The circuit accordingto one of claims 1 to 6, characterized in that the elementary activecomponent is an MOS transistor.
 9. The circuit according to one ofclaims 1 to 6, characterized in that the elementary active component isa JFET transistor.
 10. The circuit according to one of the precedingclaims, characterized in that the device forms an analog memory cell.11. The circuit according to one of claims 1 to 9, characterized in thatthe storage device comprises several adjacent elementary activecomponents associated with several buried capacitive elementarytrenches, respectively, in respective electrical contact with severalelementary wells, said lower region of the substrate forming anisolating well with respect to the rest of the substrate, so as to forman analog memory plane which can be deleted by applying a chosen voltageto the isolating well.
 12. The circuit according to one of claims 1 to9, characterized in that the storage device comprises several adjacentelementary active components associated with several buried capacitiveelementary trenches, respectively, in respective electrical contact withseveral elementary wells, so as to form a light sensor, each pixel ofwhich is formed by an elementary active component and by the associatedelementary trench.
 13. A process for fabricating an integrated circuitcomprising a semiconductor device for storing charge having at least oneelementary active component and one elementary storage capacitor,characterized in that: a) an initial single-crystal substrate (1)locally having a capacitive elementary trench emerging at the surface ofthe initial substrate and forming a discontinuity in the crystal latticeis prepared, b) the initial substrate is recessed at the elementarytrench, c) the crystal lattice is amorphized around the periphery of therecess, d) a layer of amorphous material having the same chemicalcomposition as that of the initial substrate is deposited on thestructure obtained in the previous step, e) the structure obtained inthe previous step is thermally annealed in order to recrystallize theamorphous material so as to be continuous with the single-crystallattice of the initial substrate, f) an upper substrate layer is grownby epitaxy, g) an elementary well located above and in contact with thecapacitive elementary trench is defined in said upper substrate layerand the elementary active component is made in the elementary well or inand on the elementary well.
 14. The process according to claim 13,characterized in that it comprises, prior or subsequent to step e), asurface planarization step.
 15. The process according to claim 14,characterized in that the planarization step comprises achemical-mechanical polishing operation.
 16. The process according toone of claims 13 to 15, characterized in that the amorphization stepcomprises localized ion implantation around the recess by means of amasking operation.
 17. The process according to one of claims 13 to 16,characterized in that in step a), a first layer (2) of a first materialand a second layer (3) of a second material are deposited in successionon the initial substrate (1), then a trench (4) is etched, which isfilled with a fill material, and in that, in step b), the first layerand an upper portion of the elementary trench fill material areselectively etched with respect to said second layer (3) so as to formlateral cavities and said recess at the crystal discontinuity, and saidsecond layer (2) is removed.
 18. The process according to claim 17,characterized in that, in step a), the filling of the elementary trenchcomprises the following steps: the walls of the elementary trench (4)are lined with oxide (8) by thermal oxidation; highly dopedpolycrystalline silicon (9) is deposited in the elementary trench (4) soas to fill it; the polycrystalline silicon (9) deposited previously isetched so that the fill level of the elementary trench (4) is below thesurface of the initial substrate (1).
 19. The process according to oneof claims 13 to 18, characterized in that the definition of theelementary well comprises the production of isolation regions,implantation and annealing.